A low-complexity implementation of a transmitter design for modern mobile radio systems for frequency modulation is provided by a ΣΔ fractional-N phase locked loop, which is also referred to below as a ΣΔ fractional-N PLL or else just as a PLL.
The PLL 10, as shown in FIG. 1, comprises a phase/frequency detector 1, a charge pump 2, a loop filter 3, a voltage-controlled oscillator 4 (VCO for short) and a frequency divider 5. Applied to one input of the PLL 10 is a reference frequency fref whose phase is compared, by means of the phase/frequency detector 1, with a phase of a frequency fdiv that results from an output frequency fvco which has been divided by a division value N. If necessary, the phase/frequency detector 1 generates an actuating signal and supplies it to the charge pump 2, which takes said actuating signal as a basis for generating a voltage U which, once filtered by means of the filter 3, is applied to the input of the voltage-controlled oscillator 4 as a tuning voltage UVCO. Said voltage-controlled oscillator, in turn, generates the output frequency fvco, which is dependent on the tuning voltage UVCO.
The frequency modulation desired is effected digitally by varying the frequency division value N with the aid of a ΣΔ modulator 6. Digital transmission data D are combined with a channel word KW using an adder 7 and are supplied to the ΣΔ modulator 6, which then uses them to determine the division value N which it supplies to the frequency divider 5. In this case, the channel word KW prescribes the channel.
When a non-integrating loop filter 3 is used, the transmission bandwidth of the phase locked loop 10 is directly proportional to the VCO gradient Kvco. The transfer function H(jω) of the closed control loop 10 is determined as follows:
                    H        (                  jω          (                      =                                          vvc                rre                            =                              N                                  1                  +                                      jωω                    ⁢                                          /                      0                                                                                                                              (        1        )            where    φvco is the phase at the PLL output,    φref is the phase at the PLL input,    ω is the angular frequency, and    N is the division value.
The cut-off frequency f0 of the −3 dB bandwidth of the PLL 10 is calculated from:
                    f0        =                              Kp            ·            R            ·            Kvco                    N                                    (        2        )            where    Kp is the phase detector gradient,    R is the loop resistance to ground, and    Kvco is the VCO gradient.
The phase detector gradient Kp is proportional to the charge pump current Icp.
The document U.S. 2002/0039050 A1 specifies a synthesizer having a charge pump in which the charge pump current is compensated for relative to the tuning curve of the VCO. In this case, the charge pump current of the charge pump (which is connected between the phase detector and the oscillator) is matched as a function of the magnitude of a frequency control signal at the input of the voltage-controlled oscillator.
The prior art has hitherto not disclosed a PLL which can be used to firmly set the DC voltage no-load gain and cut-off frequency across all channels and all tolerances.